
1
LTC1741
1741f
FEATURES
DESCRIPTIO
U
APPLICATIO S
U
BLOCK DIAGRA
W
12-Bit, 65Msps Low Noise ADC
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Sample Rate: 65Msps
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72dB SNR and 85dB SFDR (3.2V Range)
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70.5dB SNR and 87dB SFDR (2V Range)
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No Missing Codes
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Single 5V Supply
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Power Dissipation: 1.275W
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Selectable Input Ranges:
±1V or ±1.6V
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240MHz Full Power Bandwidth S/H
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Pin Compatible Family
25Msps: LTC1746 (14-Bit), LTC1745(12-Bit)
50Msps: LTC1744 (14-Bit), LTC1743(12-Bit)
65Msps: LTC1742 (14-Bit), LTC1741(12-Bit)
80Msps: LTC1748 (14-Bit), LTC1747(12-Bit)
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48-Pin TSSOP Package
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Telecommunications
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Receivers
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Cellular Base Stations
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Spectrum Analysis
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Imaging Systems
, LTC and LT are registered trademarks of Linear Technology Corporation.
The LTC
1741 is an 65Msps, sampling 12-bit A/D con-
verter designed for digitizing high frequency, wide dy-
namic range signals. Pin selectable input ranges of
±1V
and
±1.6V along with a resistor programmable mode
allow the LTC1741’s input range to be optimized for a wide
variety of applications.
The LTC1741 is perfect for demanding communications
applications with AC performance that includes 72dB
SNR and 85dB spurious free dynamic range. Ultralow jitter
of 0.15psRMS allows undersampling of IF frequencies of up
to 70MHz with excellent noise performance. DC specs
include
±1 LSB INL and ±0.8LSB DNL over temperature.
The digital interface is compatible with 5V, 3V, 2V and
LVDS logic systems. The ENC and ENC inputs may be
driven differentially from PECL, GTL and other low swing
logic families or from single-ended TTL or CMOS. The low
noise, high gain ENC and ENC inputs may also be driven
by a sinusoidal signal without degrading performance. A
separate output power supply can be operated from 0.5V
to 5V, making it easy to connect directly to any low voltage
DSPs or FIFOs.
The TSSOP package with a flow-through pinout simplifies
the board layout.
65Msps, 12-Bit ADC with a
±1V Differential Input Range
12-BIT
PIPELINED ADC
12
S/H
AMP
±1V
DIFFERENTIAL
ANALOG INPUT
AIN
+
AIN
–
SENSE
VCM
4.7
F
DIFF AMP
REFLA
REFHB
GND
1741 BD
ENC
4.7
F
1
F1F
0.1
F
0.1
F
REFHA
REFLB
BUFFER
RANGE
SELECT
2.35VREF
CORRECTION
LOGIC AND
SHIFT
REGISTER
OUTPUT
LATCHES
CONTROL LOGIC
OVDD
VDD
OGND
0.5V
TO 5V
5V
0.1
F
1
F
1
F
1
F
D11
D0
CLKOUT
OF
ENC
DIFFERENTIAL
ENCODE INPUT
OE
MSBINV
0.1
F